Wafer alignment mark scheme

ABSTRACT

A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide light directed to a backside of the wafer. The light detection device is configured to detect reflected light intensity from the backside of the wafer to find a position of at least one wafer alignment mark formed on the back side of the wafer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of U.S. Provisional PatentApplication Ser. No. 61/616,975, filed on Mar. 28, 2012, which isincorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates generally to an integrated circuit andmore particularly to a wafer alignment mark.

BACKGROUND

For an integrated circuit fabrication process, some wafers have a notchfor wafer alignment. For such a wafer, the wafer is rotated 360° in somecases to find the wafer notch for alignment. However, the wafer notchmay result in random solvent splash on the wafer during a wafer edgecleaning process, which is a defect source and can induce yield penalty.Also, such solvent splash can induce arcing effect during an etchingprocess of the wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference is now made to the following descriptions taken in conjunctionwith the accompanying drawings, in which:

FIG. 1A is a schematic diagram of an exemplary wafer with waferalignment marks according to some embodiments;

FIG. 1B is a cross-section view of an exemplary wafer with waferalignment marks according to some embodiments;

FIG. 1C is a schematic diagram of an exemplary wafer alignment markdetection setup according to some embodiments;

FIGS. 2A-2D are plots of detected light intensity versus wafer positionfor the exemplary wafer alignment marks in FIG. 1A according to someembodiments;

FIG. 3 is a schematic diagram of exemplary wafer alignment mark shapesaccording to some embodiments; and

FIG. 4 is a flowchart of an exemplary method of wafer aligning usingwafer alignment marks in FIG. 1A according to some embodiments.

DETAILED DESCRIPTION

The making and using of various embodiments are discussed in detailbelow. It should be appreciated, however, that the present disclosureprovides many applicable inventive concepts that can be embodied in awide variety of specific contexts. The specific embodiments discussedare merely illustrative of specific ways to make and use, and do notlimit the scope of the disclosure.

In addition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.Moreover, the formation of a feature on, connected to, and/or coupled toanother feature in the present disclosure that follows may includeembodiments in which the features are formed in direct contact, and mayalso include embodiments in which additional features may be formedinterposing the features, such that the features may not be in directcontact. In addition, spatially relative terms, for example, “lower,”“upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,”“top,” “bottom,” etc. as well as derivatives thereof (e.g.,“horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of thepresent disclosure of one features relationship to another feature. Thespatially relative terms are intended to cover different orientations ofthe device including the features.

FIG. 1A is a schematic diagram of an exemplary wafer 102 with waferalignment marks 104 according to some embodiments. The wafer 102 haswafer alignment marks 104 at a back side 103. There are four exemplarywafer alignment marks 104 centered at positions evenly distributed alongthe edge of the wafer 102 as shown in FIG. 1A: a first wafer alignmentmark 104 a having one recess (opening, hole, or cut), a second waferalignment mark 104 b having two recesses, a third wafer alignment mark104 c having three recesses, and a fourth wafer alignment mark 104 dhaving four recesses. The wafer 102 comprises silicon or any othersuitable material. The wafer alignment marks 104 are formed on thewafer's backside by laser or etching, for example.

The four wafer alignment marks 104 a, 104 b, 104 c, and 104 d are formedcentered at 0°, 90°, 180°, and 270° respectively along the edge of thewafer 102. Therefore, by rotating the wafer 102 by 90°, one of the fourwafer alignment marks will be detected to find the alignment position.If a different number of wafer alignment marks 104 are used, thepositions of the wafer alignment marks 104 can be evenly distributed bydividing 360° by the number of the wafer alignment marks 104. Forexample, if there are three wafer alignment marks 104, they can bedistributed at 0°, 120°, 240°. In this case, the wafer can be rotated by120° to find one of the wafer alignment marks 104 to find the alignmentposition. In other embodiments, the wafer alignment marks 104 can bedistributed unevenly depending on the applications.

The size of the wafer alignment marks 104 are from (1 mm×1 mm) to (5mm×5 mm) in some embodiments. The wafer alignment marks 104 have a depthof 0.12 μm in one example. The shape of the wafer alignment marks 104can be different shapes, such as a circle, triangle, square or any otherpolygon, for example.

FIG. 1B is a cross-section view of exemplary wafer 102 with waferalignment marks 104 according to some embodiments. The wafer 102 has afront side 101 used as a main surface for integrated circuit formationand the backside 103. The wafer alignment marks 104 are formed on thebackside 103 of the wafer 102. The wafer 102 has a thickness 106 rangingfrom 100 μm to 300 μm in some embodiments. The wafer alignment marks 104(recesses) have a depth 105 ranging from 100 nm to 200 nm in someembodiments. If the depth 105 is less than 100 nm, the detection of thewafer alignment marks 104 may need higher sensitivity to recognize thedifference in reflected light intensity due to the wafer alignment marks104. If the depth 105 is greater than 200 nm, particles may remain inthe wafer alignment marks 105.

FIG. 1C is a schematic diagram of an exemplary wafer alignment markdetection setup 107 according to some embodiments. A light source 108such as laser and a light detection device 110 such as charge-coupleddevice (CCD) sensor are located under the wafer 102. As the wafer 102 isrotated by a rotation device 112 for a specified angle, lighttransmitted from the light source 108 is directed to the wafer backside103 and reflected to the light detection device 110. The light detectiondevice 110 such as a CCD sensor collects the light intensitydistribution to find the wafer alignment position. In some embodiments,the detected light intensity is reduced at the wafer alignment mark 104positions to find the alignment positions.

By using the wafer alignment mark 104 formed on the backside 103 of thewafer 102, solvent splash impact is reduced during the wafer edgecleaning process. With four wafer alignment mark 104 evenly spaced asshown in FIG. 1A, the alignment mark search time (e.g., rotating thewafer 90°) is reduced 75% compared to finding a notch by rotating thewafer 360°. Therefore, the wafer process yield time is improved.

FIGS. 2A-2D are plots 200 a-200 d of detected light intensity versuswafer position for the exemplary wafer alignment marks in FIG. 1Aaccording to some embodiments. In FIG. 2A, the (light) intensity plot200 a shows finding the position I of the first wafer alignment mark 104a in FIG. 1A with one recess (opening, hole, or cut). As the wafer 102is rotated 90 degrees, the detected light intensity is reduced atposition I due to the first wafer alignment mark 104 a. Since thedetected intensity is reduced one time, the position I is found as thefirst wafer alignment mark 104 a. The position I can be used for thewafer alignment. In some embodiments, a computer, a processor, or amemory can be used to monitor the detected intensity or save theposition for alignment.

In FIG. 2B, the (light) intensity plot 200 b shows finding the positionII of the second wafer alignment mark 104 b in FIG. 1A with tworecesses. As the wafer 102 is rotated 90 degrees, the detected lightintensity is reduced two times centered at the position II due to thesecond wafer alignment mark 104 b. The position II is found as thesecond wafer alignment mark 104 b. The position II can be used for thewafer alignment.

In FIG. 2C, the (light) intensity plot 200 c shows finding the positionIII of the third wafer alignment mark 104 c in FIG. 1A with threerecesses. As the wafer 102 is rotated 90 degrees, the detected lightintensity is reduced three times centered at the position III due to thethird wafer alignment mark 104 c. The position III is found as the thirdwafer alignment mark 104 c. The position III can be used for the waferalignment.

In FIG. 2D, the (light) intensity plot 200 d shows finding the positionIV of the fourth wafer alignment mark 104 d in FIG. 1A with fourrecesses. As the wafer 102 is rotated 90 degrees, the detected lightintensity is reduced four times centered at the position IV due to thefourth wafer alignment mark 104 d. The position IV is found as thefourth wafer alignment mark 104 d. The position IV can be used for thewafer alignment.

Even though the number of recesses is counted to find and identify waferalignment marks 104 in the examples, different shapes or patternscomprising multiple small recesses can be used for the wafer alignmentmarks 104 with the light detection device 110 recognizing the shapes orpatterns.

FIG. 3 is a schematic diagram of exemplary wafer alignment mark shapesaccording to some embodiments. FIG. 3 shows different wafer alignmentmark shapes 302, 304, 306, and 308 comprising multiple small recesses orholes (dots). The light detection device 110 detects (identifies orrecognizes) the shapes or patterns and find the alignment position insome embodiments. Any other shapes or patterns can be used for the waferalignment marks 104 in FIG. 1A in other embodiments.

FIG. 4 is a flowchart of an exemplary method of wafer alignment usingwafer alignment marks 104 in FIG. 1A according to some embodiments. Atstep 402, light is transmitted from a light source to a backside of awafer. At step 404, the wafer is rotated for a specified angle, e.g.,90°. The rotated angle is 360° divided by the number of wafer alignmentmarks in some embodiments. In some embodiments, if the distribution ofalignments marks is uneven, the specified angle is different than 360°divided by the number of wafer alignment marks. At step 406, reflectedlight from the backside of the wafer is detected by a light detectiondevice. At step 408, a position of at least one wafer alignment markthat is formed on the backside of the wafer is found.

According to some embodiments, a wafer alignment apparatus includes alight source, a light detection device, and a rotation device configuredto rotate a wafer. The light source is configured to provide lightdirected to a backside of the wafer. The light detection device isconfigured to detect reflected light intensity from the backside of thewafer to find a position of at least one wafer alignment mark formed onthe back side of the wafer.

According to some embodiments, a method includes transmitting light froma light source to a backside of a wafer. The wafer is rotated for aspecified angle. Reflected light from the backside of the wafer isdetected by a light detection device. A position of at least one waferalignment mark formed on the backside of the wafer is found.

According to some embodiments, a wafer includes a front side used as amain surface for integrated circuit formation, a back side, and at leastone wafer alignment mark formed on the back side. The at least one waferalignment mark is configured to change a light intensity reflected fromthe back side in order to find a position of the at least one waferalignment mark.

A skilled person in the art will appreciate that there can be manyembodiment variations of this disclosure. Although the embodiments andtheir features have been described in detail, it should be understoodthat various changes, substitutions and alterations can be made hereinwithout departing from the spirit and scope of the embodiments.Moreover, the scope of the present application is not intended to belimited to the particular embodiments of the process, machine,manufacture, and composition of matter, means, methods and stepsdescribed in the specification. As one of ordinary skill in the art willreadily appreciate from the disclosed embodiments, processes, machines,manufacture, compositions of matter, means, methods, or steps, presentlyexisting or later to be developed, that perform substantially the samefunction or achieve substantially the same result as the correspondingembodiments described herein may be utilized according to the presentdisclosure.

The above method embodiment shows exemplary steps, but they are notnecessarily required to be performed in the order shown. Steps may beadded, replaced, changed order, and/or eliminated as appropriate, inaccordance with the spirit and scope of embodiment of the disclosure.Embodiments that combine different claims and/or different embodimentsare within the scope of the disclosure and will be apparent to thoseskilled in the art after reviewing this disclosure.

What is claimed is:
 1. A wafer alignment apparatus, comprising: a lightsource; a light detection device; and a rotation device configured torotate a wafer, wherein the light source is configured to provide lightdirected to a backside of the wafer, the light detection device isconfigured to detect reflected light intensity from the backside of thewafer to find a position of at least one wafer alignment mark formed onthe back side of the wafer.
 2. The wafer alignment apparatus of claim 1,wherein the position of the at least one wafer alignment mark is foundby recognizing reduced light intensity detected by the light detectiondevice.
 3. The wafer alignment apparatus of claim 1, wherein the waferis rotated for a specified angle depending on a number of the at leastone alignment mark.
 4. The wafer alignment apparatus of claim 3, whereinthe specified angle is given as 360° divided by the number of the atleast one wafer alignment mark.
 5. The wafer alignment apparatus ofclaim 3, wherein the number of the at least one alignment mark is fourand the specified angle is 90°.
 6. The wafer alignment apparatus ofclaim 1, wherein each of the at least one wafer alignment mark includesat least one recess.
 7. The wafer alignment apparatus of claim 6,wherein the at least one recess has a depth ranging from 100 nm to 200nm.
 8. The wafer alignment apparatus of claim 6, wherein a number of theat least one recess is from one to a number of the at least one waferalignment mark.
 9. The wafer alignment apparatus of claim 1, whereineach of the at least one wafer alignment mark comprises multiplerecesses.
 10. The wafer alignment apparatus of claim 1, whereinpositions of multiple wafer alignment marks of the at least one waferalignment mark are evenly distributed along an edge of the wafer. 11.The wafer alignment apparatus of claim 1, wherein the light detectiondevice is a charge-coupled device (CCD) sensor.
 12. A method,comprising: transmitting light from a light source to a backside of awafer; rotating the wafer for a specified angle; detecting reflectedlight from the backside of the wafer by a light detection device; andfinding a position of at least one wafer alignment mark formed on thebackside of the wafer.
 13. The method of claim 12, wherein finding theposition of the at least one wafer alignment mark comprises recognizingreduced light intensity detected by the light detection device.
 14. Themethod of claim 12, wherein the wafer is rotated for a specified angledepending on a number of the at least one alignment mark.
 15. The methodof claim 14, wherein the specified angle is given as 360° divided by thenumber of the at least one wafer alignment mark.
 16. The method of claim14, wherein the number of the at least one alignment mark is four andthe specified angle is 90°.
 17. The method of claim 12, wherein each ofthe at least one wafer alignment mark comprises multiple recesses. 18.The method of claim 12, wherein positions of multiple wafer alignmentmarks of the at least one wafer alignment mark are evenly distributedalong an edge of the wafer.
 19. The method of claim 12, wherein thelight detection device is a charge-coupled device (CCD) sensor.
 20. Awafer, comprising: a front side for integrated circuit formation; a backside; and at least one wafer alignment mark formed on the back side,wherein the at least one wafer alignment mark is configured to change alight intensity reflected from the back side in order to find a positionof the at least one wafer alignment mark.